Recently, multimedia processing functions such as images and sounds, and digital devices such as digital versatile disk (DVD) recorders incorporating wired and wireless communication functions have been generally used. These devices are demanded to process at the same time plural real-time tasks such as codec processing, wireless protocol processing, and user interface processing. Therefore, a data processor to control the above devices is usually realized as a system LSI in which plural CPUs (central processing unit), DSP (digital signal processor), a hardware accelerator to perform specific processing are interconnected by on-chip buses.
AS one configuration of high-speed on-chip buses, a split bus transaction non-blocking type bus is known which multiplexes and pipelines bus transactions in an axial direction in time. As a reference document, for example, patent document 1 describes bus configuration of this type.
However, the bus of this type generally allows relatively easy management for data transfer throughput, but has difficulty in guaranteeing transfer latency directly related to real-time capability. Therefore, by including plural sets of on-chip buses to be allocated according to the priority of data transfer, a design to significantly increase a hardware scale because of multiplexing of data transfers in a space direction has been demanded.
[Patent Document 1] Japanese patent laid-open No. 2004-530197